Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika Strona 2
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Contents
About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function.....1-1
40- and 100-Gbps Ethernet MAC and PHY IP Core Supported Features...........................................1-3
40-100GbE IP Core Device Family and Speed Grade Support..............................................................1-4
Device Family Support....................................................................................................................1-4
40-100GbE IP Core Device Speed Grade Support...................................................................... 1-5
IP Core Verification.....................................................................................................................................1-6
Simulation Environment................................................................................................................ 1-7
Hardware Testing.............................................................................................................................1-7
Performance and Resource Utilization.....................................................................................................1-7
Resource Utilization for 40GbE IP Cores.....................................................................................1-7
Resource Utilization for 100GbE IP Cores.................................................................................1-12
Release Information...................................................................................................................................1-18
Getting Started.................................................................................................... 2-1
Installing and Licensing IP Cores..............................................................................................................2-2
OpenCore Plus IP Evaluation........................................................................................................ 2-2
Specifying the 40-100GbE IP Core Parameters and Options................................................................ 2-3
IP Core Parameters......................................................................................................................................2-3
Files Generated for the 40-100GbE IP Core...........................................................................................2-10
Simulating the IP Core..............................................................................................................................2-10
Integrating Your IP Core in Your Design..............................................................................................2-11
Pin Assignments.............................................................................................................................2-11
External Transceiver Reconfiguration Controller.....................................................................2-11
Placement Settings for the 40-100GbE IP Core.........................................................................2-14
40-100GbE IP Core Testbenches.............................................................................................................2-14
Testbenches with Adapters...........................................................................................................2-15
Testbenches without Adapters.....................................................................................................2-18
Understanding the Testbench Behavior.....................................................................................2-19
Simulating the 40-100GbE IP Core With the Testbenches..................................................................2-20
Generating the 40-100GbE Testbench........................................................................................2-21
Simulating with the Modelsim Simulator...................................................................................2-21
Simulating with the NCSim Simulator....................................................................................... 2-21
Simulating with the VCS Simulator............................................................................................ 2-21
Testbench Output Example: 40GbE IP Core with Adapters................................................... 2-21
Testbench Output Example: 100GbE IP Core with Adapters.................................................2-23
Compiling the Full Design and Programming the FPGA....................................................................2-24
Initializing the IP Core..............................................................................................................................2-24
Functional Description....................................................................................... 3-1
High Level System Overview......................................................................................................................3-2
40-100GbE MAC and PHY Functional Description.............................................................................. 3-2
TOC-2
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
Altera Corporation
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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