Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika Strona 191
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Date ACDS
Version
Changes
• Added link to Low Latency 40-100GbE IP core user guide in About the
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function and
in Device Family Support.
• Added new 10GBASE-KR Registers appendix to provide the 10GBASE-
KR PHY register information that forms the basis for the 40GBASE-
KR4 Registers descriptions. This information is correct at the time of
publication but may lag updates to the source document, the Altera
Transceiver PHY IP Core User Guide.
• Removed mention of register 0x0C2 bit [8] from 40GBASE-KR4
Registers on page 3-92 because this register bit is now described in the
10GBASE-KR PHY register listing.
• Clarified that the tx_ready signal might an inadequate indication that
the IP core is ready to accept and handle data on the TX client interface
with adapters. Following reset, the application should not send data on
this interface until after the lanes_deskewed signal is asserted,
indicating the IP core can safely transmit packets on the Ethernet link.
In the case of the TX client interface without adapters, the application
should also wait until after the lanes_deskewed signal is asserted.
Notice appears in 40-100GbE IP Core TX Data Bus with Adapters
(Avalon-ST Interface) and in 40-100GbE IP Core TX Data Bus
Without Adapters (Custom Streaming Interface).
• Corrected lists of testbench files in Testbenches with Adapters and in
Testbenches without Adapters. The new lists are correct for the IP core
v13.1 and later.
• Corrected assorted typos.
March 2014
v13.1
(2014.03.04
)
• Corrected device support list:
• To include support for Stratix V GS devices.
• To specify Final support for Stratix V devices.
• Included "40-100GbE IP Core TX Data Bus with Adapters (Avalon-ST
Interface)" section inadvertently omitted from previous version of user
guide.
• In "Frame Check Sequence (CRC-32) Insertion" section, corrected CRC_
CONFIG register bit that controls TX CRC insertion.
• Removed inconsistent statement in "40-100GbE IP core CRC Checking"
section that incorrectly indicated that CRC aligns with EOP.
• In "Statistics Counters Interface" section, fixed descriptions of the size-
based frame counting signals.
• In "Order of Transmission" section, improved figures showing byte
order on the Avalon-ST interface with and without preamble pass-
through enabled.
• In "About the 40- and 100-Gbps Ethernet MAC and PHY MegaCore
Function" chapter, removed mention of 4 and 20 virtual lanes, and
replaced with information correct for the Avalon-ST client-side
interface. The virtual lanes are relevant only on the Ethernet link.
• In "OpenCore Plus Time-Out Behavior" section, removed mention of
nonexistent local_ready signal.
D-2
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide Revision
History
UG-01088
2014.12.15
Altera Corporation
Additional Information
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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