Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika Strona 112
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rc_busy[3:0]
Input
40GBASE-KR4 reconfiguration
interface. These signals are
present only in 40GBASE-KR4
variations for which you turn on
Enable KR4 Reconfiguration.
All 40GBASE-KR4 variations are
in Duplex mode.
The lt_start_rc, main_rc,
post_rc, pre_rc, and tap_to_
upd signals are present only if
you turn on Enable Link
Training.
The dfe_start_rc, dfe_mode,
ctle_start_rc, ctle_rc, and
ctle_mode signals are present
only if you turn on Enable RX
equalization.
lt_start_rc[3:0]
Output
main_rc[23:0]
Output
post_rc[19:0]
Output
pre_rc[15:0]
Output
tap_to_upd[11:0]
Output
seq_start_rc[3:0]
Output
dfe_start_rc[3:0]
Output
dfe_mode[7:0]
Output
ctle_start_rc[3:0]
Output
ctle_rc[15:0]
Output
ctle_mode[7:0]
Output
pcs_mode_rc[5:0]
Output
en_lcl_rxeq[3:0]
Output
rxeq_done[3:0]
Input
reco_mif_done
Input
Related Information
• Resets on page 3-54
Overview of IP core reset access. Includes list of reset signals and recommended reset sequence.
• Transceiver PHY Serial Data Interface on page 3-45
• MAC to PHY Connection Interface on page 3-43
Describes the tx_lanes_stable PHY output signal.
• Clocks on page 3-51
Overview of IP core clocks. Includes list of clock signals and recommended and required frequencies.
• 40-100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) on page 3-9
• Pause Control and Generation Interface on page 3-35
• Link Fault Signaling Interface on page 3-37
• Statistics Counters Interface on page 3-39
• Statistics Registers on page 3-108
• Lane to Lane Deskew Interface on page 3-43
Describes the lanes_deskewed PHY output signal.
UG-01088
2014.12.15
Signals of MAC and PHY Variations Without Adapters
3-65
Functional Description
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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