Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Instrukcja Użytkownika Strona 190
- Strona / 199
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Additional Information
D
2014.12.15
UG-01088
Subscribe
Send Feedback
40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide
Revision History
Table D-1: Document Revision History
Summarizes the new features and changes in the user guide for the 40- and 100-Gbps Ethernet MAC and PHY
MegaCore function.
Date ACDS
Version
Changes
2014.12.15 v14.1
• Updated release-specific information for the software release v14.1.
• Updated for new Quartus II IP Catalog, which replaces the MegaWizard
Plug-In Manager starting in the Quartus II software v14.0. Changes are
located primarily in Getting Started. Reordered the chapter to
accommodate the new descriptions.
• Removed OpenCore Plus exception for 40GBASE-KR4 feature.
OpenCore Plus evaluation is available for this feature in the IP core
version 14.0 and later.
• Moved licensing information and the description of the OpenCore Plus
evaluation feature to Getting Started.
• Corrected description of IPG_DEL_PERIOD register in MAC Feature
Configuration Registers.
• Corrected statements that the pause signals are available only in 40-
100GbE IP core variations without adapters. Pause signals have been
available in IP core variations with and without adapters since the IP
core v12.0. Changes are located in Pause Control and Generation
Interface, in Conditions Triggering XOFF Frame Transmission , in
Conditions Triggering XON Frame Transmission , in Signals of MAC
and PHY Variations With Adapters, and in Pause Registers.
• Clarified that while the IP core is paused it can still transmit pause
frames, in Congestion and Flow Control Using Pause Frames.
• Clarified reset requirements in Resets.
©
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera 40-Gbps Ethernet MAC and PHY MegaCore Function
(39 strony)© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.021 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji