Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Pobierz pdf (Strona 128)

Low Latency 40-100GbE IP Core MAC Configuration Registers

The MAC configuration registers control the following MAC features in the RX and TX datapaths:

• Fault link signaling on the Ethernet link (TX)

• Local and remote fault status signals (RX)

• CRC forwarding (RX)

• Inter-packet gap IDLE removal (TX)

• Maximum frame sizes for the CNTR_RX_OVERSIZE and CNTR_TX_OVERSIZE counters (RX and TX)

The fault link signaling and fault status signal registers are documented separately. Refer to Related Links

below.

Table 3-24: TX MAC Configuration Registers

This table documents the non-fault link signaling registers in the TX MAC address space. The

LINK_FAULT_CONFIG register at address 0x405 is documented with the link fault signaling registers. The

LINK_FAULT_CONFIG register is available only if you turn on Enable link fault generation in the Low Latency

40-100GbE parameter editor.

Address Name Bit Description HW Reset

Value

Access

0x400 TXMAC_REVID [31:0] TX MAC revision ID. 0x020620

0x401 TXMAC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW

0x402 TXMAC_NAME_0 [31:0] First 4 characters of IP core variation

identifier string "40gMACTxCSR" or

"100gMACTxCSR".

0x403 TXMAC_NAME_1 [31:0] Next 4 characters of IP core variation

identifier string "40gMACTxCSR" or

"100gMACTxCSR".

0x404 TXMAC_NAME_2 [31:0] Final 4 characters of IP core variation

identifier string "40gMACTxCSR" or

"100gMACTxCSR".

0x406

IPG_COL_REM

[15:0] Specifies the number of IDLE columns to be

removed in every Alignment Marker period to

compensate for alignment marker insertion.

You can program this register to a larger value

than the default value, for clock compensa‐

tion.

This register is not present if you set the value

of the Average interpacket gap parameter to

Disable deficit idle counter in the Low

Latency 40-100GbE parameter editor.

(decimal)

100GbE

variations;

4 in

40GbE

variations

UG-01172

2015.05.04

Low Latency 40-100GbE IP Core MAC Configuration Registers

3-83

Functional Description

Altera Corporation

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