Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Strona 146
- Strona / 196
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Address Name- Description Access
0x924 CNTR_RX_
OVERSIZE_LO
Number of oversized frames (frames with more bytes than
the number specified in the MAX_RX_SIZE_CONFIG register)
received (lower 32 bits)
RO
0x925 CNTR_RX_
OVERSIZE_HI
Number of oversized frames (frames with more bytes than
the number specified in the MAX_RX_SIZE_CONFIG register)
received (upper 32 bits)
RO
0x926 CNTR_RX_MCAST_
DATA_OK_LO
Number of valid multicast frames received, excluding
control frames (lower 32 bits)
RO
0x927 CNTR_RX_MCAST_
DATA_OK_HI
Number of valid multicast frames received, excluding
control frames (upper 32 bits)
RO
0x928 CNTR_RX_BCAST_
DATA_OK_LO
Number of valid broadcast frames received, excluding
control frames (lower 32 bits)
RO
0x929 CNTR_RX_BCAST_
DATA_OK_HI
Number of valid broadcast frames received, excluding
control frames (upper 32 bits)
RO
0x92A CNTR_RX_UCAST_
DATA_OK_LO
Number of valid unicast frames received, excluding
control frames (lower 32 bits)
RO
0x92B CNTR_RX_UCAST_
DATA_OK_HI
Number of valid unicast frames received, excluding
control frames (upper 32 bits)
RO
0x92C CNTR_RX_MCAST_
CTRL_LO
Number of valid multicast frames received, excluding data
frames (lower 32 bits)
RO
0x92D CNTR_RX_MCAST_
CTRL_HI
Number of valid multicast frames received, excluding data
frames (upper 32 bits)
RO
0x92E CNTR_RX_BCAST_
CTRL_LO
Number of valid broadcast frames received, excluding data
frames (lower 32 bits)
RO
0x92F CNTR_RX_BCAST_
CTRL_HI
Number of valid broadcast frames received, excluding data
frames (upper 32 bits)
RO
0x930 CNTR_RX_UCAST_
CTRL_LO
Number of valid unicast frames received, excluding data
frames (lower 32 bits)
RO
0x931 CNTR_RX_UCAST_
CTRL_HI
Number of valid unicast frames received, excluding data
frames (upper 32 bits)
RO
0x932 CNTR_RX_PAUSE_LO Number of valid pause frames received (lower 32 bits) RO
0x933 CNTR_RX_PAUSE_HI Number of valid pause frames received (upper 32 bits) RO
UG-01172
2015.05.04
RX Statistics Registers
3-101
Functional Description
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Instrukcja Użytkownika
(413 strony)
(413 strony)
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI4-St Instrukcja Użytkownika
(231 strony)
(231 strony)
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Instrukcja Użytkownika
(783 strony)
(783 strony)
Urządzenia pomiarowe Altera PCI Development Kit, Cyclone II Edition Getting St Instrukcja Użytkownika
(40 strony)
(40 strony)
Urządzenia pomiarowe Altera PCI Express Development Kit, Stratix II GX Edition Instrukcja Użytkownika
(36 strony)
(36 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.023 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji