Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Pobierz pdf (Strona 96)

Arria 10 Transceiver Reconfiguration Interface

Arria 10 variations provide a dedicated Avalon-MM interface, called the Arria 10 transceiver reconfigura‐

tion interface, to access the transceiver registers. You access the Arria 10 Native PHY IP core registers

through this dedicated interface and not through the IP core general purpose control and status interface.

The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an

embedded processor or JTAG Avalon master to this bus to access the registers of the embedded Arria 10

Native PHY IP core.

Table 3-13: Avalon-MM Arria 10 Reconfiguration Interface Signals

The reconfig_clk clocks the signals on the Low Latency 40-100GbE IP core Arria 10 transceiver reconfiguration

interface. The synchronous reconfig_reset reset signal resets the interface.

Signal Name Direction Description

reconfig_address [11:0]

(40GbE and CAUI-4)

reconfig_address [13:0]

(100GbE)

Input Address for reads and writes

reconfig_read Input Read command

reconfig_write Input Write command

reconfig_writedata [31:0] Input Data to be written

reconfig_readdata [31:0] Output Read data

reconfig_waitrequest Output Interface busy signal

The Arria 10 reconfiguration interface is designed to operate at a low frequencies, typically 100 MHz so

that the user's Arria 10 transceiver reconfiguration logic does not compete for resources with the

surrounding high speed datapath.

Related Information

Avalon Interface Specifications

For more information about the Avalon-MM protocol, including timing diagrams, refer to the Avalon

Memory-Mapped Interfaces chapter.

Arria 10 Transceiver PHY User Guide

Information about the Arria 10 Native PHY IP core hard PCS registers that you can program through the

Arria 10 transceiver reconfiguration interface.

Arria 10 Transceiver Registers

Information about the Arria 10 transceiver registers.

Clocks

You must set the transceiver reference clock (clk_ref) frequency to a value that the IP core supports. The

Low Latency 40-100GbE IP core supports clk_ref frequencies of 644.53125 MHz ±100 ppm and

UG-01172

2015.05.04

Arria 10 Transceiver Reconfiguration Interface

3-51

Functional Description

Altera Corporation

Send Feedback

1 2 ... 91 92 93 94 95 96 97 98 99 100 101 ... 195 196

Komentarze do niniejszej Instrukcji

Brak uwag

Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Strona 96

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore