Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Pobierz pdf (Strona 98)

Signal Name Description

tx_serial_clk[3:0] (for

40GbE and CAUI-4 variations

that target an Arria 10 device)

tx_serial_clk[9:0] (for

standard 100GbE variations

that target an Arria 10 device)

These input clocks are present only in variations that target an Arria 10

device. They are part of the external PLL interface to these variations.

Each clock targets a single transceiver PHY link. You must drive these

clocks from one or more TX transceiver PLLs that you configure

separately from the Low Latency 40-100GbE IP core.

Table 3-15: Clock Outputs

Describes the output clocks that the IP core provides. In most cases these clocks participate in internal clocking of

the IP core as well.

Signal Name Description

clk_txmac

The TX clock for the IP core is clk_txmac. The TX MAC clock frequency is 312.5

MHz for 40GbE IP core variations and 390.625 MHz for 100GbE IP core

variations.

If you turn on Use external TX MAC PLL in the LL 40-100GbE parameter editor,

the clk_txmac_in input clock drives clk_txmac.

clk_rxmac The RX clock for the IP core is clk_rxmac. The RX MAC clock frequency is 312.5

MHz for 40GbE IP core variations and 390.625 MHz for 100GbE IP core

variations.

This clock is only reliable when rx_pcs_ready has the value of 1. The IP core

generates clk_rxmac from a recovered clock that relies on the presence of

incoming RX data.

clk_rx_recover RX recovered clock. This clock is available only if you turn on Enable SyncE in the

LL 40-100GbE parameter editor.

The expected usage is that you drive the TX transceiver PLL reference clock with a

filtered version of clk_rx_recover, to ensure the receive and transmit functions

remain synchronized in your Synchronous Ethernet system.

UG-01172

2015.05.04

Clocks

3-53

Functional Description

Altera Corporation

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Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Strona 98