Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Instrukcja Użytkownika Strona 129
- Strona / 196
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Address Name Bit Description HW Reset
Value
Access
0x407
MAX_TX_SIZE_
CONFIG
[15:0] Maximum size of Ethernet frames for CNTR_
TX_OVERSIZE.
If the IP core transmits an Ethernet frame of
size greater than the number of bytes specified
in this register, and the IP core includes TX
statistics registers, the IP core increments the
64-bit CNTR_TX_OVERSIZE register.
9600
(decimal)
RW
Table 3-25: RX MAC Configuration Registers
This table documents the non-fault link signaling registers in the RX MAC address space. The local and remote
fault status register at address 0x508 is documented with the link fault signaling registers. The local and remote
fault status register is available only if you turn on Enable link fault generation in the Low Latency 40-100GbE
parameter editor.
Address Name Bit Description HW
Reset
Value
Access
0x500 RXMAC_REVID [31:0] RX MAC revision ID. 0x0206
2015
RO
0x501 RXMAC_SCRATCH [31:0] Scratch register available for testing. 32'b0 RW
0x502 RXMAC_NAME_0 [31:0] First 4 characters of IP core variation identifier
string "40gMACRxCSR" or "100gMACRxCSR".
RO
0x503 RXMAC_NAME_1 [31:0] Next 4 characters of IP core variation identifier
string "40gMACRxCSR" or "100gMACRxCSR".
RO
0x504 RXMAC_NAME_2 [31:0] Final 4 characters of IP core variation identifier
string "40gMACRxCSR" or "100gMACRxCSR".
RO
0x506
MAX_RX_SIZE_
CONFIG
[15:0] Maximum size of Ethernet frames for CNTR_RX_
OVERSIZE and for rx_error[3] or l<n>_rx_
error[3] and for .the RxOctetsOK register.
If the IP core receives an Ethernet frame of size
greater than the number of bytes specified in this
register, and the IP core includes RX statistics
registers, the IP core increments the 64-bit CNTR_
RX_OVERSIZE register.
An Ethernet frame of size greater than the number
of bytes specified in this register is considered
oversized and therefore does not contribute to the
value in the RxOctetsOK register.and does cause the
assertion of rx_error[3] or l<n>_rx_error[3].
9600
(decim
al)
RW
3-84
Low Latency 40-100GbE IP Core MAC Configuration Registers
UG-01172
2015.05.04
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
Powiązane produkty i podręczniki dla Urządzenia pomiarowe Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Instrukcja Użytkownika
(413 strony)
(413 strony)
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI4-St Instrukcja Użytkownika
(231 strony)
(231 strony)
Urządzenia pomiarowe Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Instrukcja Użytkownika
(783 strony)
(783 strony)
Urządzenia pomiarowe Altera PCI Development Kit, Cyclone II Edition Getting St Instrukcja Użytkownika
(40 strony)
(40 strony)
Urządzenia pomiarowe Altera PCI Express Development Kit, Stratix II GX Edition Instrukcja Użytkownika
(36 strony)
(36 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.020 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji