Altera MAX 10 Clocking and PLL Instrukcja Użytkownika Pobierz pdf (Strona 37)

The ALTPLL IP core does not have a dedicated output enable port. You can disable the PLL output using

the areset signal to disable the PLL output counters.

Guideline: PLL Cascading

Consider the following guidelines when cascading PLLs:

• Set the primary PLL to low bandwidth to help filter jitter. Set the secondary PLL to high bandwidth to

track the jitter from the primary PLL. You can view the Quartus II software compilation report file to

ensure the PLL bandwidth ranges do not overlap. If the bandwidth ranges overlap, jitter peaking can

occur in the cascaded PLL scheme.

Note: You can get an estimate of the PLL deterministic jitter and static phase error (SPE) by using the

TimeQuest Timing Analyzer in the Quartus II software. Use the SDC command

derive_clock_uncertainty to generate a report titled PLLJ_PLLSPE_INFO.txt in your

project directory. Then, use set_clock_uncertainty command to add jitter and SPE

values to your clock constraints.

• Keep the secondary PLL in a reset state until the primary PLL has locked to ensure the phase settings

are correct on the secondary PLL.

• You cannot connect any of the inclk ports of any PLLs in a cascaded scheme to the clock outputs

from PLLs in the cascaded scheme.

Related Information

PLL Cascading on page 2-26

Guideline: Clock Switchover

Use the following guidelines to design with clock switchover in PLLs:

• Clock loss detection and automatic clock switchover requires that the frequency difference between

inclk0 and inclk1 is within 20% range. Failing to meet this requirement causes the clkbad[0] and

clkbad[1] signals to function improperly.

• When using manual clock switchover, the frequency difference between inclk0 and inclk1 can be

more than 20%. However, differences between the two clock sources (frequency, phase, or both) can

cause the PLL to lose lock. Resetting the PLL ensures that the correct phase relationships are

maintained between the input and output clocks.

• Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start the manual

clock switchover event. Failing to meet this requirement causes the clock switchover to malfunction.

• Applications that require a clock switchover feature and a small frequency drift must use a low-

bandwidth PLL. When referencing input clock changes, the low-bandwidth PLL reacts slower than a

high-bandwidth PLL. When the switchover happens, the low-bandwidth PLL propagates the stoppage

of the clock to the output at a slower speed than the high-bandwidth PLL. The low-bandwidth PLL

filters out jitter on the reference clock. However, be aware that the low-bandwidth PLL also increases

lock time.

• After a switchover occurs, there might be a finite resynchronization period for the PLL to lock onto a

new clock. The exact amount of time it takes for the PLL to relock depends on the PLL configuration.

UG-M10CLKPLL

2015.05.04

Guideline: PLL Cascading

3-3

MAX 10 Clocking and PLL Design Considerations

Altera Corporation

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