Altera MAX 10 Clocking and PLL Instrukcja Użytkownika Strona 48
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Programmable Bandwidth with Advanced Parameters
An advanced level of control is also possible for precise control of the PLL loop filter characteristics. This
level allows you to explicitly select the following advanced parameters:
• Charge pump current (charge_pump_current)
• Loop filter resistance (loop_filter_r)
• Loop filter capacitance(loop_filter_c)
This option is intended for advanced users who know the exact details of their PLL configuration. You
can use this option if you understand the parameters well enough to set them optimally. The files
generated are not intended to be reused by the ALTPLL IP core parameter editor. After the ALTPLL IP
core output files are specified using the advanced parameters, the Quartus II compiler cannot change
them. For example, the compiler cannot perform optimization. Thus, your design cannot benefit from
improved algorithms of the compiler. The Quartus II compiler cannot select better settings or change
some settings that the ALTPLL IP core parameter editor finds to be incompatible with your design.
The parameter settings to generate output files using advanced PLL parameters are located on the Inputs/
Lock page of the ALTPLL IP core parameter editor.
Turn on Create output file(s) using the 'Advanced' PLL parameters to enable the feature.
When you turn on this option, the generated output files contain all of the initial counter values used in
the PLL. You can use these values for functional simulation in a third-party simulator.
These parameter settings create no additional top-level ports.
Related Information
• Programmable Bandwidth on page 2-19
• Charge Pump and Loop Filter on page 4-13
Provides more information about the PLL components to update PLL bandwidth in real time.
• Programmable Bandwidth Parameter Settings on page 6-2
PLL Dynamic Reconfiguration Implementation
To reconfigure the PLL counters, perform the following steps:
1. Assert the scanclkena signal at least one scanclk cycle prior to shifting in the first bit of scandata
(Dn).
2. Shift the serial data (scandata) into the scan chain on the second rising edge of scanclk.
3. After all 144 bits have been scanned into the scan chain, deassert the scanclkena signal to prevent
inadvertent shifting of bits in the scan chain.
4. Assert the configupdate signal for one scanclk cycle to update the PLL counters with the contents of
the scan chain.
The scandone signal goes high indicating that the PLL is being reconfigured. A falling edge indicates
that the PLL counters have been updated with new settings.
5. Reset the PLL using the areset signal if you make any changes to the M, N, post-scale output C
counters, or the I
CP
, R, and C settings.
6. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.
4-10
Programmable Bandwidth with Advanced Parameters
UG-M10CLKPLL
2015.05.04
Altera Corporation
MAX 10 Clocking and PLL Implementation Guides
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Clock Networks Overview 5
- Internal Oscillator Overview 5
- PLLs Overview 5
- • PLL cascading 6
- • Reference clock switchover 6
- Features 7
- Clock Resources 8
- Global Clock Network Sources 8
- Pin GCLK 9
- Global Clock Control Block 10
- Input Description 11
- Related Information 12
- Clock Enable Signals 13
- PLL Architecture 14
- UG-M10CLKPLL 15
- 2015.05.04 15
- PLL Features 16
- PLL Locations 16
- Clock Pin to PLL Connections 18
- PLL Control Signals 19
- Clock Feedback Modes 20
- Source Synchronous Mode 21
- No Compensation Mode 21
- Normal Mode 22
- PLL External Clock Output 23
- ADC Clock Input from PLL 25
- Spread-Spectrum Clocking 25
- PLL Programmable Parameters 25
- Programmable Phase Shift 26
- Clock Switchover 28
- Manual Clock Switchover 31
- PLL Cascading 32
- PLL Reconfiguration 32
- Considerations 35
- PLLs Design Considerations 36
- Guideline: PLL Cascading 37
- Guideline: Clock Switchover 37
- ALTCLKCTRL IP Core 39
- Search for installed IP cores 40
- ALTPLL IP Core 43
- Block Name 50
- Number of Bits 50
- Counter Control Bit Total 50
- 3. Ignore this directory 55
- ALTPLL_RECONFIG IP Core 56
- Internal Oscillator IP Core 59
- ALTCLKCTRL IP Core References 64
- ALTCLKCTRL Ports and Signals 65
- ALTPLL IP Core References 67
- Parameter Value Description 68
- ALTPLL Ports and Signals 72
- Port Name 73
- Condition Description 73
- ALTPLL_RECONFIG Parameters 77
- Parameter Value Decription 85
- Date Version Changes 86
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