Altera MAX 10 Clocking and PLL Instrukcja Użytkownika Pobierz pdf (Strona 75)

Port Name

(11)

Condition Description

locked

Optional This output port acts as an indicator when the PLL

has reached phase-locked. The locked port stays

high as long as the PLL is locked, and stays low

when the PLL is out-of-lock.

The number of cycles needed to gate the locked

signal is based on the PLL input clock. The gated-

lock circuitry is clocked by the PLL input clock. The

maximum lock time for the PLL is provided in the

MAX 10 Device Datasheet.

Take the maximum lock time of the PLL and divide

it by the period of the PLL input clock. The result is

the number of clock cycles needed to gate the

locked signal.

The lock signal is an asynchronous output of the

PLL. The PLL lock signal is derived from the

reference clock and feedback clock feeding the

phase frequency detector (PFD) as follows:

• Reference clock = Input Clock/N

• Feedback clock = VCO/M

The PLL asserts the locked port when the phases

and frequencies of the reference clock and feedback

clock are the same or within the lock circuit

tolerance. When the difference between the two

clock signals goes beyond the lock circuit tolerance,

the PLL loses lock.

phasedone

Optional This output port indicates that dynamic phase

reconfiguration is completed.

When phasedone signal is asserted, it indicates to

core logic that the phase adjustment is complete and

PLL is ready to act on a possible second adjustment

pulse. This signal asserts based on internal PLL

timing and deasserts on rising edge of SCANCLK.

scandataout

Optional The data output for the serial scan chain.

You can use the scandataout port to determine

when PLL reconfiguration completes. The last

output is cleared when reconfiguration completes.

scandone

Optional This output port indicates that the scan chain write

operation is initiated.

The scandone port goes high when the scan chain

write operation initiates, and goes low when the

scan chain write operation completes.

(11)

Replace the brackets, [], in the port name with an integer to get the exact name (for example, c0 and c1).

UG-M10CLKPLL

2014.12.15

ALTPLL Ports and Signals

6-9

ALTPLL IP Core References

Altera Corporation

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