Altera SerialLite II IP Core Instrukcja Użytkownika Strona 13
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1–8 Chapter 1: About This MegaCore Function
Installation and Licensing
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
Installation and Licensing
The SerialLite II MegaCore function is part of the MegaCore IP Library, which is
distributed with the Quartus II software and downloadable from the Altera
website,
www.altera.com.
You can use Altera's free OpenCore Plus evaluation feature to evaluate the MegaCore
function in simulation and in hardware before you purchase a license. You need to
purchase a license for the MegaCore function only when you are satisfied with its
functionality and performance, and you want to take your design to production.
After you purchase a license for the SerialLite II MegaCore function, you can request a
license file from the Altera website at www.altera.com/licensing and install it on your
computer. When you request a license file, Altera emails you a license.dat file. If you
do not have internet access, contact your local Altera representative.
Asymm
Rx
4 Packet Data 1 No No No 1604 9 11 195 1250
Asymm
Rx
4 Packet Data 2 No No No 2559 23 16 177 3125
Broad-
cast Rx
4 Streaming Data 1 No No No 561 0 0 187 1250
Broad-
cast Rx
4 Streaming Data 2 No No No 729 0 0 200 3125
Broad-
cast Rx
8 Streaming Data 2 No No No 1359 0 0 181 3125
Notes to Table 1–4:
(1) A transfer size of 1 is used for 1,250 Mbps and 2 is used for 3,125 Mbps.
(2) Total throughput equals the value in the Throughput column multiplied by the value in the Number of Lanes column.
Table 1–4. Performance for Stratix GX (Part 3 of 3)
Parameters
LEs
Memory
Blocks
f
MAX
(MHz)
Throughp
ut
Mbps
(2)
Data
Flow
Number
of
Lanes
Data Type
Packet
Type
Transfer
Size
(1)
CRC
Flow
Contro
l
Retry
- on-
Error
M51
2
M4K
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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