Altera SerialLite II IP Core Instrukcja Użytkownika Strona 27
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3–4 Chapter 3: Parameter Settings
Physical Layer Configuration
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
■ If you select a reference clock frequency that is not equal to the
data rate/(transfer size) * 10, the Clock Compensation option is disabled if the
Receiver only port type option is turned on.
Port Type
The Port Type parameter offers three options: Bidirectional, Transmitter only, and
Receiver only. If you turn on the Bidirectional option, you must specify values for
Transmitter Settings and Receiver Settings. Under Transmitter Settings, you need to
specify the Number of lanes, and select whether or not to enable the Scramble and
Broadcast mode. Under Receiver Settings, you must specify the settings for the
Number of lanes, and select whether or not to enable the De-Scramble option. If you
turn on Transmitter only option, you must specify values for Transmitter Settings
only, and if you turn on Receiver only option, you must specify values for Receiver
Settings only.
The Number of lanes parameter dictates the number of serial links, essentially the
number of external inputs and outputs (I/Os) for the MegaCore function.
If you set the Number of lanes for the transmitter and receiver settings to the same
value, you configure the MegaCore function to operate in symmetric, bidirectional
mode. Refer to Figure 3–2 and Figure 3–3 on page 3–5.
If you set the Port Type to Receiver only or Transmitter only, you configure the
MegaCore function to operate in unidirectional mode, transmitter, or receiver only.
Refer to Figure 3–4 and Figure 3–5 on page 3–6.
If you set the Port Type to Bidirectional, but have the number of lanes set to a value
other than zero, but not equal to the other function’s value, you configure the
MegaCore function to operate in asymmetric mode. Refer to Figure 3–6 and
Figure 3–7 on page 3–7.
Figure 3–2. Symmetric Mode Block Diagram
Notes to Figure 3–2:
(1) A full line indicates a mandatory lane.
(2) A dashed line indicates an optional lane.
One or more lanes
(up to N)
FPGA 1
Light-weight
Linklayer
PHY
Layer
FPGA 2
Light-weight
Linklayer
PHY
Layer
Atlantic
Interface
CDR
SERDES
CDR
SERDES
One or more lanes
(up to N)
Atlantic
Interface
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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