Altera SerialLite II IP Core Instrukcja Użytkownika Pobierz pdf (Strona 98)

5–12 Chapter 5: Testbench

Testbench Components Description

SerialLite II MegaCore Function January 2014 Altera Corporation

User Guide

A value of one causes the model to generate data intended for a priority port, so that

Atlantic

dav

signal is ignored for all but the first transfer of a packet. A value of zero

causes the model to generate data intended for a data port, so

dav

is always obeyed.

defparam agen_dat_dut.PRIORITY=0;

defparam agen_pri_dut.PRIORITY=1;

– PORT_NAME

A string used to distinguish between verbose messages coming from multiple

instances of AGEN.

defparam agen_dat_dut.PORT_NAME = "AGEN_DAT_DUT";

defparam agen_pri_sis.PORT_NAME = "AGEN_PRI_SIS";

VHDL

The VHDL version of the

AGEN

module generates Atlantic data for the SerialLite II

demonstration testbench (

agen_dat_dut

agen_dat_sis

). The data generated is based

on an incrementing pattern.

The first element (at SOP) contains a decoded packet size for the packet. Once the

packet is transmitted, the packet size count increases by one for the next packet so that

successively larger packets are sent.

The AGEN generator sends packets until the internal packet count reaches the value

of the

packets_to_end

input integer. Inner packet gaps can be optionally enabled by

driving the

ipg

input to the module with a one. Doing so changes the behavior of the

Atlantic write enable so that it is controlled by the output of a pseudo random

generator. Verbose mode for the utility can be enabled by setting the

verbose

integer

in the generic map to one.

AMON

This testbench includes separate versions of the

AMON

module for Verilog HDL and

VHDL.

Verilog HDL

This Verilog HDL version of the

AMON

module monitors the Atlantic data received

(instances:

amon_dat_dut

amon_pri_dut

amon_dat_sis

amon_pri_sis

, and so on).

The data pattern received must be based on a LFSR that has produced a predictable

but non-incrementing pattern.

The

AMON

monitor does the following basic checks:

■ Data checking: checks that the received data follows the LFSR pattern

■ id checking: checks that the packet identifier (first byte of each packet) is an

incrementing number.

■ Number of packets checking: checks that the expected number of regular data or

high priority packets have been received. The expected number of packets is set

via tasks.

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 109 110

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