Altera SerialLite II IP Core Instrukcja Użytkownika Strona 79
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Oceniono. / 5. Na podstawie oceny klientów
Chapter 4: Functional Description 4–25
Signals
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Table 4–7 on page 4–25 shows the Atlantic interface signals.
f For more information on this interface, refer to the FS13: Atlantic Interface.
1 These signals are only present when the Link Layer mode is enabled and the Atlantic
FIFO buffer is used.
1 There are no specific requirements for Atlantic clocks (
rxrdp_clk
,
rxhpp_clk
,
txrdp_clk
and
txhpp_clk
) as they are all system dependent. The Atlantic clocks at the
read side must be fast enough to prevent backpressure which decreases bandwidth
efficiency.
gxb_powerdown
(5)
Input —
Transceiver block reset and power down. This
signal resets and powers down all circuits in the
transceiver block. This does not affect the refclk
buffers and reference clock lines. All the
gxb_powerdown
input signals of cores placed in
the same transceiver block should be tied
together.The
gxb_powerdown
signal should be tied
low or should remain asserted for at least 2ms
whenever it is asserted.
Notes to Table 4–6:
(1) rxnl is the receive number of lanes; txnl is the transmit number of lanes.
(2) srx is the transfer size × the receive number of lanes.
(3) recon_quad is the total number of Quads being used.
(4) If the
altgx_reconfig
block is not used, the signal will not toggle (set to a fixed value) and thus is not on any clock domain. If the
altgx_reconfig
block is used, this signal is on the
reconfig_clk
domain.
(5) This signal is removed in configurations targeted for Arria V and Stratix V devices due to the exclusion of hard transceivers.
Table 4–6. Transceiver Megafunction Signals (Part 3 of 3)
Signal
(1)
,
(2)
Direction Clock Domain Description
Table 4–7. Atlantic Interface Signals (Part 1 of 3)
Signal Direction Clock Domain Description
rxrdp_clk
(1)
Input — Atlantic receive regular data port clock.
txrdp_clk
Input — Atlantic transmit regular data port clock.
rxhpp_clk
(1)
Input — Atlantic receive high priority port clock.
txhpp_clk
Input — Atlantic transmit high priority port clock.
rxrdp_ena
(1)
Input
rxrdp_clk
Enable signal on the Atlantic interface. Indicates that
the data is to be read on the next clock cycle.
rxrdp_dav
(1)
Input
rxrdp_clk
Input (No FIFO buffer) determines whether flow
control is required on this port. When this signal is
low, the fill level has been breached. When this signal
is high, the FIFO buffer has enough space for more
words.
rxrdp_dav
(1)
Output
rxrdp_clk
Output (With FIFO buffer) represents the buffer’s fill
level. This signal is high when the level is above FTL
or if an EOP is in the buffer.
rxrdp_val
(1)
Output
rxrdp_clk
The output data is valid.
rxrdp_sop
(1)
Output
rxrdp_clk
Start of packet indicator on the Atlantic interface.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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