Altera SerialLite II IP Core Instrukcja Użytkownika Strona 97
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Oceniono. / 5. Na podstawie oceny klientów
Chapter 5: Testbench 5–11
Testbench Components Description
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
If the
iptg
task is called, idle cycles are inserted between write operations. The
probability of idles between write cycles decreases with larger values of
prob
.
–
verbose(bit_value)
The
verbose
task enables or disables the display of AGEN verbose messages.
–
corrupt_sop
The
corrupt_sop
task corrupts the start of packet (SOP) of the next packet. When
called, it waits for the SOP and corrupts it (makes SOP==0). All the subsequent
packets are not corrupted.
–
corrupt_eop
The
corrupt_eop
task corrupts the end of packet (EOP) of the next packet. When
called, it waits for the EOP and corrupts it (makes EOP==0). All the subsequent
packets are not corrupted.
AGEN Parameters
The MegaWizard Plug-In Manager sets these parameters based on the selected
configuration, and the parameters are fixed for a given SerialLite II configuration.
1 These parameters are documented for reference purposes only. Do not modify them.
– PRIORITY
Table 5–3. iptg Task Field Description
Field Location
in Task
Field Valid Values Description
1
prob
0 to 0xFFFF_FFFF
(integer)
The
prob
field sets the probability of a transaction gap. The
probability decreases with a larger value of
prob
.
Before each transaction, a random number between 0 and
prob
is generated and compared to
prob/2
. If they match,
a random gap is inserted; if not, no gap is inserted.
2
min
0 to 0xFFFF_FFFF
(cycles)
The
min
field sets the minimum value, in Atlantic clock
cycles, for a random gap between AGEN write transactions.
3
max
0 to 0xFFFF_FFFF
(cycles)
The
max
field sets the maximum value, in Atlantic clock
cycles, for a random gap between AGEN write transactions.
A
max
field greater than or equal to the
min
field is required.
When
max==min
, no gap occurs.
Table 5–4. verbose Task Field Description
Field Location
in Task
Field Valid Values Description
1
bit_value
1'b0 or 1'b1
Setting
bit_value
to 1, enables the display of verbose
messages.
Setting
bit_value
to 0, disables the display of verbose
messages (default).
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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