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January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
5. Testbench
General Description
This chapter describes the features and applications of the SerialLite II testbench to
help you successfully design and verify your design implementation.
This demonstration testbench is available in Verilog HDL for all configurations and in
VHDL for restricted configurations. The testbench shows you how to instantiate a
model in a design, it stimulates the inputs and checks the outputs of the interfaces of
the SerialLite II MegaCore function, demonstrating basic functionality.
The demonstration testbench is generic and can be used with any Verilog HDL or
VHDL simulator. The scripts allow you to run the testbench in the standard edition
(SE) or the Altera edition (AE) of the ModelSim
®
software.
Figure 5–1 on page 5–3 shows the block diagram of the SerialLite II testbench. The
shaded blocks are provided with the SerialLite II testbench.
1 For Arria V and Stratix V configurations, you are required to edit the dynamically
generated testbench to include the Custom PHY IP core instantiation. For more
information about this configuration, refer to “MegaCore Configuration for Arria V,
Cyclone V, and Stratix V Devices” on page 4–19.
Features
The SerialLite II testbench includes the following features:
■ Easy to use simulation environment for any standard Verilog HDL or VHDL
simulator. For VHDL configurations where the VHDL demonstration testbench is
not generated, a mixed language simulator is required to simulate the Verilog
HDL testbench with the VHDL IP Functional Simulation models.
■ Open source Verilog HDL or VHDL testbench files.
■ Flexible SerialLite II functional model to verify your application that uses any
SerialLite II MegaCore function.
■ Simulates all basic SerialLite II transactions.
SerialLite II Testbench Files
The Verilog HDL demonstration testbench and associated scripts are generated when
you create a MegaCore function variation in the MegaWizard Plug-In Manager, as
described in “Generate Files” on page 2–6.
The VHDL demonstration testbench and the scripts to run it are generated when you
create a MegaCore function variation that meets the following criteria:
■ The language is VHDL.
■ Broadcast mode is disabled.
■ The data type is packets (streaming mode is disabled).
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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