Altera SerialLite II IP Core Instrukcja Użytkownika Strona 37
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3–14 Chapter 3: Parameter Settings
Link Layer Configuration
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
6. If the timer expires three times in succession, a link error is declared and the link is
restarted. You can control the Timeout limit in the SerialLite II parameter editor,
and it is good practice not to set the time-out to be too long so the system does not
have to wait too long for such situations to resolve. However, do not set the
Timeout to be too short because then the system always times out and the link
never remains up. The time-out value is based primarily on the round trip latency
(that is, from the time a packet is sent to when the
ACK
is returned to that
transmitter). The exact value of the round trip latency is undetermined, pending
device characterization, but a value of 1,024 columns is recommended.
Implementation of the retry-on-error mechanism is optional for the priority port. If
the Retry-on-error parameter is turned off, no segment acknowledgments are
generated or expected, and all segments are transmitted without any
acknowledgements from the receiver.
Table 3–4 shows the retry-on-error options for the priority data port.
Retry-on-error Responses
Table 3–5 summarizes the response to various transmission errors.
Table 3–4. Retry-on-error Options (Priority Data Port Only)
Option Description
Turned on
Logic is created to acknowledge segments and retransmit segments when errors
occur. Eight transmit segment buffers are created. Available only if the priority
data port is enabled.
Turned off
Logic is not created to acknowledge segments. Available only if the priority data
port is enabled. This is the default setting.
Table 3–5. Retry-on-error Responses
Error Response
Invalid 8b/10b codes groups Far end transmitter issues
NACK
Running disparity errors Far end transmitter issues
NACK
Unsupported valid code groups Far end transmitter issues
NACK
CRC errored segments with {EGP} sequence Far end transmitter issues
NACK
Out of order segment Far end transmitter issues
NACK
Out of order acknowledgment Near end transmitter starts re-send
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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