Altera SerialLite II IP Core Instrukcja Użytkownika Strona 88
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5–2 Chapter 5: Testbench
Testbench Specifications
SerialLite II MegaCore Function January 2014 Altera Corporation
User Guide
■ Data packets are selected. (Priority packets are disabled.)
■ The number of Rx lanes and Tx lanes is the same.
■ The Rx buffer size is not equal to zero.
The SerialLite II testbench comprises the following files:
■ Verilog HDL or VHDL top-level testbench file: <variation_name>_tb.v or
<variation_name>_tb.vhd
■ Verilog HDL or VHDL IP functional simulation model of the device under test
(DUT): <variation_name>.vo or .vho
■ Verilog HDL or VHDL IP functional simulation model of the SISTER MegaCore
function used as a bus functional model for testing the DUT:
<variation_name>_sister_slite2_top.vo or .vho
1 All utilities are included in the testbench file: <variation_name>_tb.v or
<variation_name>_tb.vhd.
Testbench Specifications
This section describes the modules used by the SerialLite II testbench. Refer to
Figure 5–1 on page 5–3 for a block diagram of the SerialLite II testbench. The
SerialLite II testbench has the following modules:
■ Atlantic
™
generators
■ Device under test (DUT)
■ Sister device
■ Atlantic monitors
■ Clock and reset generator
■ Pin monitors
If your application requires a feature that is not supported by the SerialLite II
testbench, you can modify the source code to add the feature. You can also modify the
existing behavior to fit your application needs.
The testbench environment (
tb
) shown in Figure 5–1 on page 5–3 generates traffic
through the Atlantic generators (
agen_dat_dut
,
agen_pri_dut
) and sends it through
the SerialLite II MegaCore function— the device under test (DUT). The SerialLite II
interface of the DUT is connected to the SerialLite II interface of a second SerialLite II
MegaCore function—the SISTER. Data flows through the SISTER MegaCore function
and is received and checked on the Atlantic interface of the SISTER MegaCore
function (
amon_dat_sis
,
amon_pri_sis
). A similar data path exists in the opposite
direction, where the SISTER's Atlantic generators (
agen_dat_sis
,
agen_pri_sis
) send
data through the SerialLite II SISTER MegaCore function to the DUT, and data is
received on the DUT's Atlantic interface (
amon_dat_dut
,
amon_pri_dut
).
Because there is no Atlantic to Atlantic verification, the received data’s integrity is
ensured in the following ways:
■ Each Atlantic generator generates a certain number of packets or streaming bytes
which the corresponding Atlantic monitor receives.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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