Altera SerialLite II IP Core Instrukcja Użytkownika Strona 32
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Chapter 3: Parameter Settings 3–9
Physical Layer Configuration
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Scramble
Scrambling the data eliminates repeating characters, which affect the EMI
substantially at high data rates. A linear feedback shift register (LSFR) is used as a
pseudo-random number generator to scramble the data, using the following
polynomial equation:
G(x) = X
16
+ X
5
+ X
4
+ X
3
+ 1
The transmitted bits are
XOR
ed with the output of the LFSR in the data stream. At the
receiver, the data stream is again
XOR
ed with an identical scrambler to recover the
original bits. To synchronize the transmitter to the receiver, the COM character
initializes the LFSR with the initial seed of
0×FFFF XOR
ed with the lane number (LN).
Scrambling is recommended for data rates greater than 3,125 Mbps, and is optional
for lower data rates (622 to 3,125 Mbps inclusive). This parameter applies only to the
transmitter, and allows for scrambling (like CRC) to be enabled in one direction only,
as required.
De-Scramble
This parameter applies only to the receiver, and allows for descrambling (like CRC) to
be enabled in one direction only, as required. Descrambling is required if the incoming
data stream is scrambled.
Broadcast Mode
If you enable the broadcast mode parameter for the transmitter, you configure the
MegaCore function to use a single shared transmitter and multiple receivers in the
master device, as shown in Figure 3–8 and Figure 3–9. The number of receivers is
determined by the number of lanes chosen for the slave receiver. The master
transmitter uses its output lanes to broadcast identical messages to all slave receivers,
and each slave responds individually by sharing the master's lanes.
Figure 3–8. Broadcast Mode Block Diagram
Master FPGA
Broadcast message
Broadcast message
Broadcast message
N-return
lanes
Shared TX
Link
RX Link 1
RX Link 2
RX Link N
Atlantic
Interface
Shared TX
PHY
RX PHY 1
RX PHY 2
RX PHY N
TX Tsv r 1
TX Tsv r 2
TX Tsv r N
RX Tsvr 1
RX Tsvr 2
RX Tsvr N
Slave FPGA N
Light-weight
Linklayer
PHY
Layer
CDR
SERDES
Atlantic
Interface
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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