Altera Avalon Verification IP Suite Instrukcja Użytkownika Pobierz pdf (Strona 118)

event_src_ready()

event_src_ready()Prototype:

Verilog HDL: N.A.

VHDL: bfm_id

Arguments:

voidReturns:

Notifies the testbench that the ready signal was asserted.Description:

VHDLLanguage support:

event_src_transaction_complete()

event_src_transaction_complete()Prototype:

Verilog HDL: N.A.

VHDL: bfm_id

Arguments:

voidReturns:

Notifies the testbench that all transactions were accepted.Description:

VHDLLanguage support:

get_response_latency()

get_response_latency()Prototype:

Verilog HDL: None

VHDL: response_latency, bfm_id, req_if(bfm_id)

Arguments:

intReturns:

Returns the response latency in cycles due to back pressure for the most recently

removed transaction.

Description:

Verilog HDL, VHDLLanguage support:

Avalon-ST Source BFM

Altera Corporation

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