Altera Avalon Verification IP Suite Instrukcja Użytkownika Pobierz pdf (Strona 135)

set_ready()

set_ready()Prototype:

Verilog HDL: read_bit

VHDL: read_bit, bfm_id, req_if(bfm_id)

Arguments:

voidReturns:

Sets the value of the interface’s ready signal. To assert back pressure, deassert this

signal. The parameter USE_READY must be set to 1 to enable the ready signal.

Description:

Verilog HDL, VHDLLanguage support:

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a fatal error has occurred. It terminates the simulation.Description:

Verilog HDLLanguage support:

signal_sink_ready_assert

signal_sink_ready_assertPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that sink_ready is asserted, turning off back pressure.Description:

Verilog HDLLanguage support:

Altera Corporation

Avalon-ST Sink BFM

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