Altera Avalon Verification IP Suite Instrukcja Użytkownika Pobierz pdf (Strona 195)

get_ci_clk_en()

void get_ci_clk_en(bit enable)Prototype:

Verilog HDL: None

VHDL: clk_en, bfm_id, req_if(bfm_id)

Arguments:

bit enableReturns:

Retrieves the clock enable signal.Description:

Verilog HDL, VHDLLanguage support:

get_instruction_a()

string get_instruction_a()Prototype:

Verilog HDL: None

VHDL: instruction_a, bfm_id, req_if(bfm_id)

Arguments:

ci_addr_tReturns:

Retrieves the instruction register file address a value.Description:

Verilog HDL, VHDLLanguage support:

get_instruction_b()

string get_instruction_b()Prototype:

Verilog HDL: None

VHDL: instruction_b, bfm_id, req_if(bfm_id)

Arguments:

ci_addr_tReturns:

Retrieves the instruction register file address b value.Description:

Verilog HDL, VHDLLanguage support:

get_instruction_c()

string get_instruction_c()Prototype:

Verilog HDL: None

VHDL: instruction_c, bfm_id, req_if(bfm_id)

Arguments:

ci_addr_tReturns:

Retrieves the instruction register file address c value.Description:

Verilog HDL, VHDLLanguage support:

Altera Corporation

Nios II Custom Instruction Slave BFM

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Altera Avalon Verification IP Suite Instrukcja Użytkownika Strona 195