Altera Avalon Verification IP Suite Instrukcja Użytkownika Pobierz pdf (Strona 47)

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a fatal error has occured in this module.Description:

Verilog HDLLanguage support:

signal_max_command_queue_size

signal_max_command_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the maximum pending transaction queue size threshold has been

exceeded.

Description:

Verilog HDLLanguage support:

signal_min_command_queue_size

signal_min_command_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the pending transaction queue size is below the minimum threshold.Description:

Verilog HDLLanguage support:

Altera Corporation

Avalon-MM Master BFM

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signal_fatal_error

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