Altera Avalon Verification IP Suite Instrukcja Użytkownika Pobierz pdf (Strona 168)

signal_grant_deasserted_while_request_remain_asserted

signal_grant_deasserted_while_request_remain_assertedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.Arguments:

voidReturns:

Triggers when the grant signal changes value from high to low while the request

signal remains asserted.

Description:

Verilog HDLLanguage support:

signal_interface_granted

signal_interface_grantedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.Arguments:

voidReturns:

Triggers when the grant signal is asserted.Description:

Verilog HDLLanguage support:

signal_max_transaction_queue_size

signal_max_transaction_queue_sizePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

None.Arguments:

voidReturns:

Triggers when the size of the pending queue exceeds the maximum size.Description:

Verilog HDLLanguage support:

Altera Corporation

Tri-State Conduit BFM

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signal_grant_deasserted_while_request_remain_asserted

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