Altera Avalon Verification IP Suite Instrukcja Użytkownika Pobierz pdf (Strona 125)

signal_response_done

signal_response_donePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the response to a driven data beat is available.Description:

Verilog HDLLanguage support:

signal_src_driving_transaction

signal_src_driving_transactionPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals when the source begins to drive a transaction to the interface.Description:

Verilog HDLLanguage support:

signal_src_not_ready

signal_src_not_readyPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the ready signal is not asserted.Description:

Verilog HDLLanguage support:

signal_src_ready

signal_src_readyPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the ready signal is asserted.Description:

Verilog HDLLanguage support:

Altera Corporation

Avalon-ST Source BFM

Send Feedback

8-13

signal_response_done

1 2 ... 120 121 122 123 124 125 126 127 128 129 130 ... 223 224

Brak uwag

Altera Avalon Verification IP Suite Instrukcja Użytkownika Strona 125